J-LINK EDU 與 J-Link BASE 完全一致、提供相同的功能!其差異在於 J-LINK EDU 每日第一次使用時,可能會遭遇彈出版權聲明畫面。
原廠連結:https://www.segger.com/j-link-edu.html
J-LINK EDU is identical to J-Link BASE and offers the same functionality. It has been designed to allow students and educational facilities as well as hobbyists access to top of the line debug probe technology.
Limitations:
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Documentation download
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J-Link EDU is delivered with the following components:
J-Link EDU | 20-pin, 0.1" target ribbon cable | USB cable |
You may use the J-Link EDU for non profit educational purposes only! Non-profit educational purposes means that you may not use the J-Link EDU and its J-Link software
Any other use of the J-Link EDU is prohibited and illegal! If there is any doubt if a certain use may be considered within the foregoing scope or whether your use of the J-Link EDU applies to an educational situation, it is strongly recommended to get in touch and consult SEGGER prior use.
For clarification purposes: A student using the J-Link EDU direct or indirect in a business or profit organization (e.g. company) is considered a violation of the scope of this agreement.
Note: Before installing the J-Link EDU software package you need to accept the Terms of use as shown on the screen below:
The following tables show the features which are included in each J-Link / J-Trace model.
Hardware features like Ethernet interface, USB full- / high-speed interface, etc. are J-Link model specific features which can not be updated or changed by software updates.
J-Link BASE | J-Link PLUS | J-Link ULTRA+ | J-Link PRO | J-Trace PRO for Cortex-M | J-Trace for Cortex-M | J-Trace ARM | |
---|---|---|---|---|---|---|---|
Download speed into RAM1 |
1.0 MByte/sec | 1.0 MByte/sec | 3.0 MByte/sec | 3.0 MByte/sec | 3.0 MByte/sec | 3.0 MByte/sec |
1.0 MByte/sec |
Max. target interface speed | 15 MHz | 15 MHz | 50 MHz | 50 MHz | 50 MHz | 25 MHz | 12 MHz |
Max. SWO speed | 7.5 MHz | 7.5 MHz | 100 MHz | 100 MHz | 100 MHz | 25 MHz | - |
USB | |||||||
Ethernet | |||||||
JTAG interface | |||||||
SWD interface | |||||||
SWO interface | |||||||
Microchip ICSP® interface |
|||||||
Renesas FINE interface | |||||||
ETM Trace | |||||||
ETB Trace |
Supported Not supported
Software features are features implemented in the software primarily on the host. Software features can either come with the J-Link or be added later using a license string from Segger.
J-Link BASE | J-Link PLUS | J-Link ULTRA+ | J-Link PRO | J-Trace PRO for Cortex-M | J-Trace for Cortex-M | J-Trace ARM | |
---|---|---|---|---|---|---|---|
GDB Server | |||||||
Flash Download2 | |||||||
Unlimited Flash Breakpoints3 | |||||||
J-Flash | |||||||
RDI | |||||||
RDDI |
Supported Optional, an additional license is required
Support for additional / new cores may be added to existing J-Link models with a new firmware version as far as the exisiting J-Link hardware allows it.
J-Link BASE | J-Link PLUS | J-Link ULTRA+ | J-Link PRO | J-Trace PRO for Cortex-M | J-Trace for Cortex-M |
J-Trace ARM | |
---|---|---|---|---|---|---|---|
ARM legacy cores | |||||||
ARM7 | |||||||
ARM9 | |||||||
ARM11 | |||||||
ARM Cortex cores | |||||||
Cortex-A5 | |||||||
Cortex-A7 | |||||||
Cortex-A8 | |||||||
Cortex-A9 | |||||||
Cortex-A12 | |||||||
Cortex-A15 | |||||||
Cortex-A17 | |||||||
Cortex-M0 | |||||||
Cortex-M0+ | |||||||
Cortex-M1 | |||||||
Cortex-M3 | |||||||
Cortex-M4 | |||||||
Cortex-M7 | |||||||
Cortex-R4 | |||||||
Cortex-R5 | |||||||
SC000 (M0 secure) | |||||||
SC300 (M3 secure) | |||||||
Microchip PIC32 | |||||||
Microchip PIC32MX | |||||||
Microchip PIC32MZ | |||||||
Renesas RX | |||||||
Renesas RX110 | |||||||
Renesas RX111 | |||||||
Renesas RX210 | |||||||
Renesas RX21A | |||||||
Renesas RX220 | |||||||
Renesas RX610 | |||||||
Renesas RX621 | |||||||
Renesas RX62G | |||||||
Renesas RX62N | |||||||
Renesas RX62T | |||||||
Renesas RX630 | |||||||
Renesas RX631 | |||||||
Renesas RX63N | |||||||
Renesas RX63T |
Debug support: Run control, memory access, etc Trace supported Not supported
1 | The download speeds listed here are the peak download speeds that can be achieved by the particular J-Link model. The actual download speed may be lower as it depends on various factors, such as, but not limited to: The selected debug interface & speed, the CPU core and its operating frequency, other devices in the JTAG chain in case JTAG is used as target interface. |
2 | Most IDEs come with their own flashloaders, so in most cases this feature is not essential for debugging your applications in flash. The J-Link flash download (FlashDL) feature is mainly used in debug environments where the debugger does not come with an own flashloader (e.g. the GNU Debugger). For more information about flash download, please refer to Flash Download. |
3 | The Unlimited Flash Breakpoint feature allows setting an unlimited number of breakpoints even if the application program is not located in RAM, but in flash memory. Without this feature, the number of breakpoints which can be set in flash is limited to the number of hardware breakpoints (typically two for ARM 7/9, six for Cortex-M3). For more information about flash breakpoints, please refer to Unlimited Flash Breakpoints. |
4 | Infineon specific single-pin debug interface. Currently available for Infineon XMC1000 series devices only. |